1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices and, more particularly, to a method for manufacturing semiconductor devices incorporating a transistor having a trench type channel.
2. Description of the Related Art
As the use of semiconductor memory devices has continued to expand in computers, telecommunications equipment and personal electronics, the demand for improved semiconductor memory devices has remained strong. From a functional point of view, preferred semiconductor memory devices will tend to be those that are reliable, capable of operating a high speed and simultaneously provide a large data storage capacity.
In order to meet these demands, the fabrication technology employed in manufacturing semiconductor memory devices has tended to focus on improving the degree of integration, the reliability and the operating speed of semiconductor memory devices. As the degree of integration increases, the surface area available for forming the individual memory cells decreases. As the cell size is reduced, the dimensions of the structural elements and patterns formed on the substrate, as well as the manufacturing process margins associated with such elements and patterns, has also been reduced.
As a result, the channel length of a cell memory cell transistor decreased to a point where leakage current presented a concern with regard to the memory cell transistor performance and reliability. In order to suppress or reduce the leakage current, various methods for lengthening the effective channel length have been proposed and utilized. One such method utilizes a trench type gate electrode in the cell transistor rather than a conventional planar type gate electrode.
FIGS. 1–5 are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device having a trench type channel. Referring to FIG. 1, a pad oxide layer (not shown) is formed on a substrate 100 with a mask layer (not shown) then being formed on the pad oxide layer. The mask layer is subsequently patterned using any conventional photolithography process to form a mask pattern (not shown) that exposes portions of the pad oxide layer. The exposed portions of the pad oxide layer and the underlying substrate 100 are then etched using the mask pattern as an etching mask to form isolation trenches having an upper width greater than a lower width.
An oxide layer (not shown) is then formed on the substrate 100 and the isolation trenches with a nitride layer (not shown) then being formed on the oxide layer. A thicker insulating layer (not shown) is then formed on the nitride layer to a thickness sufficient to fill the isolation trenches. Upper portions of the insulating layer, the nitride layer and the oxide layer are then removed to planarize the surface and expose regions of the substrate 100 between isolation trench structures 140 that include an oxide layer pattern 110, a liner nitride layer pattern 120 and an insulating layer pattern 130. The isolation trench structures 140 will tend to exhibit an upper width greater than a lower width generally corresponding to the shape of the isolation trench. An active region A may be defined in a portion of the substrate 100 arranged between adjacent isolation trench structures 140.
Referring to FIG. 2, a first channel trench 150 is then formed by removing an upper portion of the substrate 100 from the active region A using a highly anisotropic etch. Conventionally, a mask pattern (not shown) will be formed on the substrate 100 to expose only a portion of the substrate in the active region. The exposed substrate 100 is then etched using the mask pattern as an etching mask to form the first channel trench 150 in the active region A.
Because the isolation trench structures 140 tend to have an upper width that is greater than their lower width, a residual portion 100a of the substrate 100 will tend to remain in region B adjacent the isolation trench structures 140 after formation of the first channel trench 150. Because the remaining portion 100a of the substrate can interfere with the subsequent formation of a memory cell transistor, allowing the remaining portion to remain in place will tend to degrade the electrical function and reliability of the resulting memory cell transistor. Accordingly, it is desirable to remove the residual portion 100a of the substrate 100 from the peripheral regions of the first channel trench 150.
Referring to FIG. 3, the remaining portion 100a of the substrate 100 may be removed using a secondary dry etch to form a second channel trench 160. However, although the conventional secondary dry etch tends to remove the majority of the residual portion 100a, a second residual tip portion 100b will tend to be formed along the periphery of the channel trench adjacent the isolation trench structures in region C. The tip portion 100b of the substrate 100 may weaken or degrade a gate oxide layer formed in the channel trench during a subsequent process.
Referring to FIG. 4, a sacrificial oxide layer (not shown) is formed on the substrate 100 and the isolation trench structures 140. The sacrificial oxide layer and a portion of the isolation trench structures 146, specifically an upper portion of the oxide layer 110, are then removed to form a third channel trench 170. The sacrificial oxide layer provides some protection for the upper surface of the isolation trench structures 140 during the etch process. Referring to FIG. 5, a gate oxide layer 180 is then formed on the exposed surfaces of substrate 100 and a gate electrode 190 is formed on the gate oxide layer 180 and the isolation trench structures 140.
However, in the conventional fabrication method, the residual portion 100a of the substrate 100 must be removed using a secondary etch process and typically a second dry etch apparatus, thus requiring an additional etch step for the formation of the channel trench.
Further, because the secondary etch process does not tend to remove all of the residual portion 100a of the substrate 100 not completely removed using the conventional secondary etch method, a smaller residual tip 100b of the substrate will tend to remain along the periphery of the channel trench. This residual tip 100b, if left in place, will tend to compromise or degrade the subsequently formed gate oxide layer 180 to a degree that lowers the performance and/or reliability of resulting memory cell transistor.